Integrated circuits often contain memory controllers for interfacing with memory. For example, a system with double data rate three synchronous dynamic random access memory (DDR3 SDRAM) may have a memory controller for interfacing with the DDR3 SDRAM. Memory controllers can operate at high frequencies (e.g., hundreds of megahertz) and transfer large quantities of data. As an example, a DDR3 memory controller operating at a clock speed of 533 MHz may transfer data at up to 34133 megabits per second (Mb/s). Due to the high clock speed and large quantities of data transferred, modern memory controllers consume a significant amount of power.
Conventional memory controllers are primarily optimized for bandwidth and latency. A conventional memory controller is typically configured to reduce the latency between a memory access request from a processing unit and a response to the memory access request. However, optimization for low latency memory accesses may result in unacceptable power consumption for the memory controller.
In an effort to reduce power consumption to acceptable levels, conventional memory controllers use brute force methods such as throttling memory accesses to reduce power consumption (i.e., directing the memory controller to process fewer memory access requests per second). Other conventional methods include reducing operational clock speed or turning off access to certain portions of system memory.